1. Field of the Invention
The present invention relates to a method of operating a semiconductor device, and more particularly, the a method of operating a silicon oxide nitride oxide semiconductor (SONOS) memory device.
A claim of priority is made to Korean Patent Application No. 10-2005-0039727, filed on May 12, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A silicon oxide nitride oxide semiconductor (SONOS) memory device is a type of non-volatile memory device.
FIG. 1 illustrates the typical structure of a SONOS memory device. Referring to FIG. 1, drain and source regions 12 and 14 are spaced apart at the surface of a substrate 10. A gate oxide layer 16 is disposed on the substrate 10 between the drain and the source region 12 and 14. A trap layer 18 is disposed on the gate oxide layer 16. The trap layer 18 is a storage node layer where bit data is recorded, and is generally formed of a nitride film (Si3N4). In a data write operation, electrons are trapped in trap sites of the trap layer 18. A barrier layer 20 is formed on the trap layer 18, and blocks an influx of electrons into a gate 22 when the electrons are trapped in the trap layer 18. The barrier layer 20 is formed of, for example, a silicon oxide film. The gate 22 is formed on the barrier layer 20. Although not illustrated, the sides of a gate stacking body including the gate oxide layer 16, the trap layer 18, the barrier layer 20, and the gate 22 are covered by a gate spacer formed of an insulation material.
In the SONOS memory device of FIG. 1, electrons are trapped in the trap layer 18 in a write operation. When the electrons are distributed over a large area of the trap layer 18, it can become difficult to reliably execute an erase operation. That is, electrons in the trap layer 18 which are trapped at the points where holes are injected can be readily removed by an erase operation, while electrons trapped where holes are not injected cannot be readily removed by the erase operation. Consequently, erase efficiency is degraded.
To reduce the size of a region where electrons are trapped in the trap layer 18, a modified SONOS memory device having a narrower trap layer has been introduced. FIG. 2 illustrates the structure of such a modified SONOS memory device.
Referring to FIG. 2, in the modified SONOS memory device, the gate is formed in a region where a portion of the trap layer 18 is formed in the SONOS memory device of FIG. 1, and thus the trap layer 18 is narrower in the SONOS memory device of FIG. 2 than in the SONOS memory device of FIG. 1.
The curves embedded in FIG. 3 illustrate the electric field intensity distributions in the trap layer 18 of the SONOS memory device of FIG. 2 during writing and erasing operations. In particular, the curve 24G denotes an electric field intensity distribution when trapping electrons in the trap layer 18 to record bit data (i.e., a write operation). The curve 26G denotes an electric field intensity distribution when injecting holes into the trap layer 18 to erase the bit data.
Referring to FIG. 3, the center of the curve 24G and the center of the curve 26G are separated from each other. Since distributions of the electrons and holes trapped in the trap layer 18 can be represented by the electric field intensities illustrated by the curves 24Ga and 26G, the displacement between the curves 24G and 26G indicates that positions where the electrons are trapped are different from positions where the holes are trapped. After being trapped in the trap layer 18, it is difficult for electrons and holes to move within the trap layer 18 such that the trapped electrons cannot be completely removed in the erase operation. As the write and erase operations are repeatedly executed, the number of electrons remaining in the trap layer 18 increases, resulting in a decreased on-cell current. Consequently, the difference between the on-cell current and an off-cell current is decreased, and as a result, the reliability of write and erase operations is decreased and device malfunctions can occur.